armv8: fsl-layerscape: Update ddr erratum a008336

DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.

Signed-off-by: Shengzhou Liu <[email protected]>
Reviewed-by: York Sun <[email protected]>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index f62b78d1021c9c783c389bf1400272118d2f564d..28928b3086450aa74fbc7a18db9448f1b684e3ea 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -58,11 +58,13 @@ static void erratum_a008336(void)
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
        eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
-       out_le32(eddrtqcr1, 0x63b30002);
+       if (fsl_ddr_get_version(0) == 0x50200)
+               out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
        eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
-       out_le32(eddrtqcr1, 0x63b30002);
+       if (fsl_ddr_get_version(0) == 0x50200)
+               out_le32(eddrtqcr1, 0x63b30002);
 #endif
 #endif
 }